When testing a device under test that outputs a serial transmission signal, a conventional test apparatus performs a clock data recovery process on the output signal to generate a sampling clock timing in synchronization with the output signal. The test apparatus acquires the output signal from the device under test based on the generated sampling clock timing and judges acceptability of the output signal. The test apparatus may use a PLL (Phase Locked Loop) circuit for this clock data recovery process, as in, for example, D. C. Keezer, D. Minier, M. Paradis, F. Binette, “Modular Extension of ATE to 5 Gbps”, USA, 2004, INTERNATIONAL TEST CONFERENCE 2004 (ITC2004), P 748-757 (Paper 26.3).
The PLL circuit, however, requires a long time to stabilize the frequency of the sampling clock. PLL circuits with high-speed responses include high-speed devices such as GaAs devices, and are therefore extremely expensive. Therefore, it is expensive for a conventional test apparatus to acquire an output signal with a high clock rate. Furthermore, the PLL circuit accumulates random jitter from the output signal, which affects the sampling clock. This makes it difficult to accurately acquire the output signal when a conventional test apparatus uses the PLL circuit for the clock data recovery process.